/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __HIUSB_ONT_H
#define __HIUSB_ONT_H

#include <linux/platform_device.h>
/*
* hiusb Host Controller Drivers
*/
#define CONFIG_HIUSB_EHCI_IOBASE       (0x10A40000)
#define CONFIG_HIUSB_EHCI_IOSIZE       (0x00010000)
#define CONFIG_HIUSB_EHCI_IRQNUM       (71)
#define CONFIG_HIUSB_EHCI_IRQNUM_5117P (68)

#define CONFIG_HIUSB_OHCI_IOBASE       (0x10A50000)
#define CONFIG_HIUSB_OHCI_IOSIZE       (0x00010000)
#define CONFIG_HIUSB_OHCI_IRQNUM       (70)
#define CONFIG_HIUSB_OHCI_IRQNUM_5117P (67)

#define CONFIG_HIUSB_XHCI_IOBASE       (0x10A50000)
#define CONFIG_HIUSB_XHCI_IOBASE_5117P (0x10600000)
#define CONFIG_HIUSB_XHCI_IOSIZE       (0x00010000)
#define CONFIG_HIUSB_XHCI_IRQNUM       (71)

#define CHIP_ID_SERIAL_VERSION_MASK    (0xfffff000)
#define CHIP_ID_SERIAL_MASK            (0xffff0000)
#define CHIP_ID_VERSION_MASK           (0xf000)
#define CHIP_ID_SUB_VERSION_MASK       (0xffffff00)
#define CHIP_ID_ALL_VERSION_MASK       (0xfffffff0)

/* SERIAL_VERSION after the mask of CHIP_ID_SERIAL_VERSION_MASK,not care the last 3 bits */
#define CHIP_ID_SD5115H                (0x51150000)
#define CHIP_ID_SD5115S                (0x51151000)
#define CHIP_ID_SD5115T                (0x51152000)

#define CHIP_ID_SD5116H                (0x51160000)
#define CHIP_ID_SD5116S                (0x51161000)
#define CHIP_ID_SD5116T                (0x51162000)
#define CHIP_ID_SD5116TV5              (0xD53EA000)
#define CHIP_ID_SD5116L                (0x51163000)

#define CHIP_ID_SD5118                 (0x51180100)
#define CHIP_ID_SD5118V2               (0x51180200)
#define CHIP_ID_SD5117H                (0x51170000)
#define CHIP_ID_SD5117L                (0x51173000)
#define CHIP_ID_SD5117P                (0x51176000)
#define CHIP_ID_SD5117V                (0x51177000)
#define CHIP_ID_SD5117V_V6             (0x87607100)
#define CHIP_ID_SD5117P_V5             (0xE536E100)
#define CHIP_ID_SD5182H_V5             (0x95409430)
#define CHIP_ID_SD5182S_V5             (0xD9969000)
#define CHIP_ID_SD5182T                (0x51822100)
#define CHIP_ID_SD5182TCS              (0x38322000)

#define CHIP_ID_SD5182H                (0x51820000)
#define CHIP_ID_SD5182S                (0x51821000)
#define CHIP_ID_SD5610H                (0x56100000)
#define CHIP_ID_SD5610T                (0x56102000)
#define CHIP_ID_SD1156H                (0x56120000)
#define CHIP_ID_SD5190                 (0x51900000)
#define CHIP_ID_SD1155H                (0x00050000)
#define CHIP_ID_SD1156E                (0x11560000)
#define CHIP_ID_SD2952H                (0x29520000)

/* serial after the mask of CHIP_ID_SERIAL_MASK,not care the last 4 bits */
#define CHIP_ID_SD5115_SERIAL          (0x51150000)
#define CHIP_ID_SD5116_SERIAL          (0x51160000)
#define CHIP_ID_SD5118_SERIAL          (0x51180000)
#define CHIP_ID_SD5117_SERIAL          (0x51170000)
#define CHIP_ID_SD5117_SERIAL_V6       (0x87600000)
#define CHIP_ID_SD5182_SERIAL          (0x51820000)
#define CHIP_ID_SD1156_SERIAL          (0x56120000)
#define CHIP_ID_SD5190_SERIAL          (0x51900000)
#define CHIP_ID_SD1155_SERIAL          (0x00050000)
#define CHIP_ID_SD1156E_SERIAL         (0x11560000)
#define CHIP_ID_SD2952_SERIAL          (0x29520000)

/* version after the mask of CHIP_ID_VERSION_MASK,not care the last 3 bits */
#define CHIP_ID_H_VERSION              (0x0000)
#define CHIP_ID_S_VERSION              (0x1000)
#define CHIP_ID_T_VERSION              (0x2000)
#define CHIP_ID_L_VERSION              (0x3000)

enum HW_CHIP_ID_E {
	HW_CHIP_ID_NONE_E = 0x0,
	HW_CHIP_ID_5115S_E,
	HW_CHIP_ID_5115H_E,
	HW_CHIP_ID_5115T_E,
	HW_CHIP_ID_5116S_E,
	HW_CHIP_ID_5116H_E,
	HW_CHIP_ID_5116T_E,
	HW_CHIP_ID_5116L_E,
	HW_CHIP_ID_5118_E,
	HW_CHIP_ID_5118V2_E,
	HW_CHIP_ID_5117H_E,
	HW_CHIP_ID_5117P_E,
	HW_CHIP_ID_5610H_E,
	HW_CHIP_ID_5610T_E,
	HW_CHIP_ID_5117V_E,
	HW_CHIP_ID_5117L_E,
	HW_CHIP_ID_5182H_E,
	HW_CHIP_ID_5182S_E,
	HAL_CHIP_ID_5117PV5,
	HAL_CHIP_ID_5182HV5,
	HAL_CHIP_ID_5182T,
	HAL_CHIP_ID_5182SV5,
	HW_CHIP_ID_5116TV5_E,
	HAL_CHIP_ID_1156H,
	HAL_CHIP_ID_1156E,
	HAL_CHIP_ID_5190,
	HAL_CHIP_ID_1155H,
	HAL_CHIP_ID_2952H,
	HW_CHIP_ID_MPW_E
};

enum USB_TYPE_ONT {
	USB_TYPE_ONT_OHCI = 0,
	USB_TYPE_ONT_EHCI,
	USB_TYPE_ONT_BUTT
};

struct hi_usb_ctrl_5115_reg_s {
	unsigned int *IOMUX_SETL0;
	unsigned int *PERI_PEREN;
	unsigned int *PERI_PEREN1;
	unsigned int *PERI_PERCTRL36;
	unsigned int *PERI_PERCTRL39;
	unsigned int *IOMUX_SEL_PHY0;
	unsigned int *IOMUX_SEL_PHY1;
	unsigned int *GPIO0_CTL;
	unsigned int *GPIO1_CTL;
	unsigned int *GPIO2_CTL;
};

struct hi_usb_ctrl_5116_reg_s {
	unsigned int *SC_PERCTRL38;  /* 0x10100134 */
	unsigned int *SC_RST_CTRL0;  /* 0x1488002c */
	unsigned int *SC_RST_CTRL1;
	unsigned int *IO_SEL0;
	unsigned int *SC_PEREN1;     /* 0x14880020 */
	unsigned int *FUNCTION_PIN_SEL;
	unsigned int *SC_PERCTRL36;
	unsigned int *SC_SYSSTAT1;
};

struct hi_usb_ctrl_5118_reg_s {
	unsigned int *SC_PER_CLK_EN1;      /* 0x14880020 */
	unsigned int *SC_PER_CLK_DIS1;     /* 0x14880024 */
	unsigned int *SC_PER_CLK_ST1;      /* 0x14880028 */
	unsigned int *SC_RST_CTRL0;        /* 0x1488002c */
	unsigned int *SC_PERCTRL62;        /* 0x101001b0 */
	unsigned int *SC_PERCTRL66;        /* 0x101001c0 */
	unsigned int *SC_PERI_PHYCFGN0;    /* 0x10a5c2c0 */
	unsigned int *SC_PERI_PHYCFGN1;    /* 0x10a5c2c4 */
	unsigned int *SC_PERI_USB3_GCTL;   /* 0x10a5c110 */
	unsigned int *FUNCTION_LVL1_SEL_L; /* 0x14900120 */
};

struct hi_usb_ctrl_5610_reg_s {
	unsigned int *pv_peren0;
	unsigned int *pv_perdis0;
	unsigned int *pv_peren1;
	unsigned int *pv_perdis1;
	unsigned int *pv_rst_ctrl0;
	unsigned int *pv_gusb3pipectrl0;
	unsigned int *pv_gusb3pipectrl1;
};

struct hi_usb_ctrl_reg_s {
	unsigned int *clk_open;    /* 0x14880020 */
	unsigned int *clk_close;   /* 0x14880024 */
	unsigned int *reset;       /* 0x1488002c */
	unsigned int *func_sel;    /* 0x14900120 */
	unsigned int *phy_cfg;     /* 0x10100154 */
};

/* when the chip(5117p) has more than 2 usb controllers, multiple drivers need to be loaded
 * in this case, each driver needs to be assigned a logic id(consistent with hisi). rate
 * is offset based on the logical id. only the products with 2 usb ports is considered now
 */
struct usb_logic_port {
	unsigned int usb2_flag;            /* USB2.0 controller data transfer flag */
	unsigned int usb2_logic_port;      /* logical port of the USB 2.0, consistent with hisi */
	unsigned int usb3_flag;            /* USB3.0 controller data transfer flag */
	unsigned int usb3_logic_port;      /* logical port of the USB 3.0, consistent with hisi */
};

struct hw_ker_chipid_info_s {
	uint32_t ui_chip_mask;        /* chip reg mask */
	uint32_t ui_chip_value;       /* masked chip reg */
	enum HW_CHIP_ID_E em_chip_id; /* chip id */
};

extern int hiusb_start_hcd_5116H(struct hi_usb_ctrl_5116_reg_s *usb_reg_ctrl);
extern int hiusb_start_hcd_5116T(struct hi_usb_ctrl_5116_reg_s *usb_reg_ctrl);
extern struct usb_logic_port *hw_usb_hcd_logic_port_get(void);

#if defined(CONFIG_ARCH_HISI) && IS_ENABLED(CONFIG_USB_HOST_ONT)
extern enum HW_CHIP_ID_E get_chip_id_ont(void);
extern int ehci_and_ohci_chip_id_check(void);
extern int hiusb_ehci_ohci_chip_id_check(struct resource *res, struct usb_logic_port *logic_port,
	struct platform_device *pdev, int type);
#else
static inline enum HW_CHIP_ID_E get_chip_id_ont(void)
{
	return HW_CHIP_ID_NONE_E;
}

static inline int ehci_and_ohci_chip_id_check(void)
{
	return 0;
}

static inline int hiusb_ehci_ohci_chip_id_check(struct resource *res,
	struct usb_logic_port *logic_port, struct platform_device *pdev, int type)
{
	return 0;
}
#endif

#if IS_ENABLED(CONFIG_USB_HOST_ONT)
extern int xhci_chip_id_check(void);
#else
static inline int xhci_chip_id_check(void)
{
	return 0;
}
#endif
#endif
